Memory Design Platform

MC2 automates the design process for standard and embedded memories. MC2 also provides a platform for seamless migration to new processes. By enhancing the overall methodology for the design and distribution of memories, MC2 ensures the reuse of a base design over many generations of sub-micron processes. Numerous users have taken advantage of MC2 capabilities for scaling their memory designs to higher densities, placing memories within their SoC, ASIC or IC designs, and making their memory design process more efficient.

Key Features

• Memory Description Language (MDL) to create Memory Architecture
• Creates Various Views
  • Physical Views - GDSII, LEF; Logical Views - SPICE, Verilog
  • Timing Models - Verilog, Synopsys, VHDL, ALF
  • Data sheet
  • Any Proprietary Model Based on Given Template
• Enables Automatic Tiling and Netlisting
• Generates Power Ring/Power Mesh
• Provides a Memory Design Framework
• Allows Via Programming, Decoder Building, ROM Programming
• Generates Internal Routes
• Contains a delay and power characterization module
• Provides GDS Import for Legacy Memory Designs
• Provides utilities: Tiling Rule Checker, MDL Debugger, Configuration Coverage
• Encrypts Memory Architecture files for Secure Distribution
• Has a Web interface for instance creation
• Automates interpolation and derating for delay/power numbers for all sizes

Manual methods of performing Memory Design are time consuming and error prone. More so, manual checks for errors and multiple regeneration of memory behavior requirement affect productivity and time-to-market. Designers need a tool that is capable of automating the process of characterization and verifying the memory based on required memory behavior.

Interra’s Characterization Systems called Touchstone automates Memory Design to rapidly provide accurate timing and power models for simulation, verification, and synthesis. Touchstone enables designers to quickly and accurately validate memory architectures that are high in performance and low in power consumption.

Easily programmable, Touchstone comes as a user-friendly platform to describe and characterize memories. Further, Touchstone can be easily integrated with MC2, Interra’s comprehensive memory development platform.

Touchstone is available on Solaris and Unix platforms.

Salient Features

• Performs Timing characterization and Power characterization
  • Setup Time Calculation, Hold Time Calculation, Recovery Time, Removal Time, Bisection Method, Calculation based on delay difference of signal arrival times on internal nodes, Delay calculation, Transition Time calculation, Width Calculation, Cycle Time Calculation
  • Static power, Dynamic power, leakage power, Power calculation based on custom mathematical expression
• Calculates capacitances and currents
• Characterizes multiple PVT corners, multiple slew-load pairs, and multiple configurations using single instruction file
• Measures setup, hold, delay, power, etc., for various slew load pairs of two or more participating signals
• Interfaces with third party simulators: HSPICE, HSIM, and SPECTRE
• Results can be generated in various formats: Tabular format (log file), raw data file format, Synopsys liberty format, or any custom format

Key Advantages

• Automates memory design and reduces manual effort in memory development
• Is independent of memory type
• Supports characterization instructions at a higher level of abstraction
• Supports parallel simulations
• Supports a modular and hierarchical mechanism for specifying memory operations for characterization
• Supports multiple simulators
• Can be easily integrated into the Design Flows and modified for user-specific requirements
• Comes with field-proven quality and tested processes that offer predictable quality
• Can be easily integrated with MC2 to provide a complete Memory Development Environment