HDL Test Suites

HDL / HVl test SuitesBeacon offers comprehensive test suites to characterize EDA tools for compliance and coverage across HDL/HVL language constructs and styles. Conforming to industry accepted definition and interpretation of language and synthesis semantics, Beacon test suites include test cases with test bench and reference golden. EDA tool developers can easily integrate Beacon with QA regression for evaluation of conformance to standards early in product development.

Key Features

  • Focused Test suite to check for language compliance and coverage
  • Unit test cases organized in sections/sub-sections based on language constructs
  • Detailed test plan with cross reference
  • Expected output
  • Easy to integrate into regression
  • Always concurrent with evolving standards/changes
Test Suite Description Datasheet
Beacon-SV SystemVerilog Test Suite - Over 5000 test cases to validate language and RTL compliance based on System Verilog IEEE-1800-2012, IEEE-1800-2009, IEEE-1800-2005 Download Datasheet
Beacon- SV MX Mixed Systems Verilog/VHDL Test Suite - Over 1,500 test cases to validate Mixed Systems Verilog/VHDL Download Datasheet
Beacon-MX Mixed Verilog/VHDL Test Suite - Over 700 test cases to validate Mixed Verilog/VHDL support in EDA tools Download Datasheet
Beacon-2k1 Verilog-2k1 Test Suite - Over 5,000 test cases to check syntax/semantics, simulation, and synthesizability based on Verilog-2001 IEEE-1364-2001 Download Datasheet
Beacon-PSL PSL Test Suite - Over 2,000 test cases in Verilog and VHDL to validate language compliance based on PSL IEEE 1850-2005 Download Datasheet
Beacon VHDL-2008 VHDL-2008 Test Suite - Over 2,000 test cases to validate language compliance based on VHDL IEEE 1076-2008. Download Datasheet
Beacon-RTL-VHDL RTL VHDL Test Suite - Over 2,100 test cases to validate synthesis styles, RTL semantics, and supported/unsupported RTL subsets based on VHDL '87 and VHDL '93 Download Datasheet
Beacon-RTL-Verilog RTL Verilog Test Suite - Over 1,500 Unit test cases to validate synthesis styles, RTL semantics, and supported/unsupported RTL subsets based on Verilog IEEE-1364-1995 Download Datasheet